MAX5938LEEE+【PDF 22/26 页】IC HOT-SWAP CTRLR -48V 16-QSOP

3) When GATE reaches the gate threshold voltage of

the power MOSFET, V

OUT

begins to ramp back

down toward V

EE

. In the interval where GATE is

below the MOSFET threshold, the MOSFET is off

and V

OUT

will droop depending on the RC time con-

stant of the load. [V

OUT

ramp]

4) When V

OUT

ramps below 74% V

CB

, the GATE is

rapidly pulled to full enhancement and the OV GATE

cycle is complete. [Full enhancement]

OV GATE Cycle to Fault management:

1) Same as step 1 above. [GATE pulldown]

2) Same as step 2 above. [GATE turn-on]

3) Same as step 3 above. [V

OUT

ramp]

4) If GATE ramps to 90% of full enhancement and

V

OUT

remains above 74% V

CB

, GATE is rapidly

pulled to V

EE

, fault management is initiated, and

PGOOD is deasserted. [Fault management]

GATE Output

GATE is a complex output structure and its condition at

any moment is dependent on various timing

sequences in response to multiple inputs. A diode to

V

EE

prevents negative excursions. For positive excur-

sions, the states are:

1) Power-off with 2V clamp.

2) 8& pulldown to V

EE.

a. Continuous during startup delay and during

fault conditions.

b. Pulsed following detected step or OV

condition.

3) Floating with 16V clamp [prior to GATE ramp].

4) 52礎 current source with 16V clamp [GATE ramp].

5) Pullup to internal 10V supply with 16V clamp [full

enhancement].

Appendix B

Step Monitor Component

Selection Analysis

As mentioned previously in the Setting the Circuit-

Breaker and Short-Circuit Thresholds section, the AC

response from V

IN

to V

OUT

is dependent on the para-

sitics of the load. This is especially true for the load

capacitor in conjunction with the power MOSFETs

R

DS(ON)

. The load capacitor (with parasitic ESR and

LSR) and the power MOSFETs R

DS(ON)

can be mod-

eled as a heavily damped second-order system. As

such, this system functions as a bandpass filter from

V

IN

to V

OUT

limiting the ability of V

OUT

to follow the V

IN

ramp. STEP_MON lags the V

IN

ramp with a first-order

RC response, while V

OUT

lags with an overdamped

second-order response.

Given a positive V

IN

ramp with a ramp rate of dV/dt, the

approximate response of V

OUT

to V

IN

is:

V

OUT

(t) = (dV/dt) x ?/DIV>

C

x (1-e

(-t / 腖,eqv)

)

+ R

DS(ON)

x I

LOAD

(Equation 1)

where ?/DIV>

C

= C

LOAD

x R

DS(ON)

.

Equation 1 is a simplification for the overdampened

second-order response of the load to a ramp input, ?/DIV>

C

= C

LOAD

x R

DS(ON)

and corresponds to the ability of

the load capacitor to transfer dV/dt current to the fully

enhanced power MOSFETs R

DS(ON)

. The equivalent

time constant of the load (?/DIV>

L,eqv

) accounts for the para-

sitic series inductance and resistance of the capacitor

and board interconnect. To characterize the load

dynamic response to V

IN

ramps, determine ?/DIV>

L,eqv

empirically with a few tests.

Similarly, the response of STEP_MON to a V

IN

ramp is:

V

STEP_MON

(t) = (dV/dt) x ?/DIV>

STEP

x (1-e

(-t / 腟TEP)

)

+ 10礎 x R

STEP_MON

(Equation 2)

where ?/DIV>

STEP

= R

STEP_MON

x C

STEP_MON.

For proper step detection, V

STEP_MON

must exceed

STEP

TH

prior to V

OUT

reaching V

SC

or within 1.4ms of

V

OUT

reaching V

CB

(or overall V

IN

ramp rates anticipat-

ed in the application). It is impossible to give a fixed set

of design guidelines that rigidly apply over the wide

array of applications using the MAX5938. There are,

however, limiting conditions and recommendations that

should be observed.

One limiting condition that must be observed is to

ensure that the STEP_MON time constant, ?/DIV>

STEP

, is not

so low that at the lowest ramp rate, the anticipated

STEP

TH

cannot be obtained. The product (dV/dt) x

?/DIV>

STEP

= ?/DIV>

STEP_MON,MAX

, is the maximum differential

voltage at STEP_MON if the V

IN

ramp were to continue

indefinitely. A related condition is setting the

STEP_MON voltage below STEP

TH

with adequate mar-

gin, V

STEP_MON

, to accommodate the tolerance of

both I

STEP_OS

(?%) and R

STEP_MON

. In determining

?/DIV>

STEP_MON

, use the 9.2礎 limit to ensure sufficient mar-

gin with worst-case I

STEP_OS

.

The margin of V

OUT

(with respect to V

SC

and V

CB

) is

set when R

CB_ADJ

is selected as described in the

Setting the Circuit-Breaker and Short-Circuit Thresholds

section. This margin may be lower at one of the temper-

ature extremes and if so, that value should be used in

the following discussion. These margins will be called

-48V Hot-Swap Controller with V

IN

Step Immunity,

No R

SENSE

, and Overvoltage Protection

22 ______________________________________________________________________________________

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